1. Field of the Invention
The present invention relates to a circuit state scan-chain for simulating and verifying IC designs, a data collection system with the scan-chain, and an emulation and verification method using the scan-chain.
2. Description of Prior Art
Time to market is an important factor for valuating competitiveness of Integrated circuit (IC) products. With enlarged scales of IC and development of IP reuse, emulation and verification for IC design need more time. Increasing efficiency of emulation and verification is an effective measure for shortening time for designing an IC product.
Emulation includes software simulation and hardware emulation. The software simulation inputs codes describing IC with hardware description language (for example RTL code) to a software simulation system, and simulates logic functions of the IC by software. The hardware emulation inputs the codes to a hardware emulation system (FPGA platform), and simulates logic functions of the IC on FPGA. The software simulation and the hardware emulation have different features. In software simulation, inside states are all recurred, and any signals of the design being tested (IC simulated by the software simulation system) can be detected. The design being tested can be analyzed in detail, but emulation speed is slow. The emulation speed of the hardware emulation system is fast, but inside signals are hard to be observed in restraint of the count of pins.
Debugging a design being tested needs to analyze in detail only a short period of time about the time at which errors are occurring. Thus only a small segment of the test item during which errors are occurring needs to be run on the software simulation system. The emulation and verification method, which combines the hardware emulation and the software simulation, assures detailed analysis of the design being tested and increases efficiency of emulation and verification. In short words, most of the design being tested runs on the hardware simulation system. The output signals of the hardware emulation system compare with standard output signals to determine whether errors occur. The behaviors during a short period of time about the time which errors occur are recurred to a software simulation system by reproducing circuit states and input sequences of the hardware emulation system. The software simulation system analyzes the test item in detail. This method has merits of both the hardware emulation and the software simulation.
Any single-clock synchronized digital system can be regarded as a huge state machine. The design being tested simulated by the hardware emulation system is such a system. Several conceptions are explained here:
Input sequence (abbreviated as input_seq): discrete sequence of input signals sampled by clock signals.
Output sequence (abbreviated as output_seq): discrete sequence of output signals sampled by clock signals.
State sequence (abbreviated as state_seq): discrete sequences of states sampled by clock signals.
Behavior function (behavior_function): a function generated by a state and a corresponding input sequence, with parameters of the current states and an input sequence, producing a state sequence and an output sequence.
The relation of the behavior_function, the state sequence, the input sequence and the output sequence is as follows:
(state_seq,output_seq)=behavior_function (init_state,input_seq).
Description of the formula above is: during a period of time, behaviors of the system (state_seq and output_seq) are determined only by behavior functions (behavior_function), initial states (init_state) and an input sequence (input_seq).
To recur the behaviors of the design being tested on a hardware emulation system to a software simulation system, the hardware emulation system requires the three sorts of information: behavior functions (behavior_function), initial states (init_state) and an input sequence (input_seq).
It is well known that, at any time, states of a single-clock synchronized IC are determined only by the stored data in an inside memory; its behaviors are determined only by all the inside terminal combinational logic; an input sequence is determined by outside.
The combinational logic on a hardware emulation system are the same as those on a software simulation system (at least under normal mode). In other words, the behaviors of the IC are the same on both of the two platforms. So, as long as the “initial states” and “input sequence” of the design being tested on the hardware emulation system are provided, the behaviors of the design being tested on the hardware emulation system can be retrieved in the software simulation system (that is, a state sequence and an output sequence). This is the basis of an emulation and verification method combining hardware emulation and software simulation.
In order to retrieve behaviors of the design being tested emulated by a hardware emulation system in a software simulation system, “initial state” and “input sequence” need to be obtained from the hardware emulation system firstly. “Input sequence” may be obtained by duplicating input of the design being tested. The essential problem is how to obtain initial states (In the art, the process of obtaining initial states is called snapshot.) Currently, a common method in the art is to connect the software simulation system and the hardware emulation system in some way, enabling circuit states to be transferred therebetween, and correspondingly, allowing emulation to switch therebetween. In a method as disclosed in U.S. Pat. No. 5,937,179 (abbreviated as 179 patent), in the case that an error is made to the hardware emulation system, the test item is stopped temporarily. A scan-chain constituted by backup registers outputs circuit states of the design being tested to the software simulation system. The test item is continued to run as of this moment in the software simulation system. The error is retrieved in the software simulation system and is analyzed (see Line 63, Column 3 to Line 39-43, Column 4 in the 179 patent). This emulation and verification method has the following drawbacks: the first, constructing a scan-chain with extra backup registers significantly increases numbers of the IC gates and cost of FPGA emulation, which is outstanding in super large scale IC design; the second, emulation is switched between the software simulation system and the hardware emulation system, and frequency of switching is so high that emulation efficiency decreases; the third, when errors occur to the hardware emulation system, the best time when the errors of the design being tested are analyzed has lapsed, and it is difficult, and even impossible, to retrieve the initial states at the moment by running the test item in the software simulation system.